Inductorless Frequency Synthesizers for Low-Cost Wireless

AbstractThe quest for ubiquitous wireless connectivity, drives an increasing demand for compact and efficient means of frequency generation. Conventional synthesizer options, however, generally trade one requirement for the other, achieving either excellent levels of efficiency by leveraging LC-oscillators, or a very compact area by relying on ring-oscillators. This chapter describes a recently introduced class of inductorless frequency synthesizers, based on the periodic realignment of a ring-oscillator, that have the potential to break this tradeoff. After analyzing their jitter-power product, the conditions that ensure optimum performance are derived and a novel digital-to-time converter range-reduction technique is introduced, to enable low-jitter and low-power fractional-N frequency synthesis. A prototype, which implements the proposed design guidelines and techniques, has been fabricated in 65 nm CMOS. It occupies a core area of 0:0275 mm$$^{2}$$ 2 and covers the 1:6-to-3:0 GHz range, achieving an absolute rms jitter (integrated from 30 kHz-to-30 MHz) of 397 fs at 2:5 mW power. With a corresponding jitter-power figure-of-merit of −244 dB in the fractional-N mode, the prototype outperforms prior state-of-the-art inductorless frequency synthesizers

Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops

This paper presents a novel time-variant model of multiplying delay-locked loops. A simple feed-forward model of the multiplexed ring oscillator mathematically describes the edge realignment process and, by providing an explicit tuning input, allows to be embedded into the time-variant multiplying delay- locked loop model without requiring approximations. Verification of the multiplexed ring oscillator model against detailed circuit simulations is presented. Closed-form expressions for the multi- plying delay-locked loop phase noise, as a function of the system parameters and noise sources, are provided

A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs

This work introduces an accurate linearized model and phase noise spectral analysis of digital bang-bang PLLs, that includes both the reference and the digitally-controlled oscillator (DCO) noise contributions. A time-domain analysis of bang-bang PLLs is leveraged to derive closed-form expressions for the integrated jitter, leading to a precise estimation of the binary phase detector (BPD) equivalent gain. The theoretical predictions differ by less than 1% from the simulation results obtained using a behavioral model, in all typical cases: dominant reference noise, dominant DCO noise, and comparable contributions. An accurate discrete-time model that takes into account the time-variant effect arising from the multirate nature of a digital phase-locked loop (DPLL) is used, along with the provided estimation of the jitter, to predict the output and input-referred phase noise spectra. An excellent match with the simulated spectra is achieved for all the different operating conditions

A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking

This article presents a fractional-N frequency synthesizer architecture that is able to overcome the limitations of conventional bang–bang phase-locked loops. A digital frequency- error recovery technique is introduced to enable fast lock, at no significant power or circuit overhead. A digital-to-time converter design with reduced static and dynamic nonlinearity is proposed, which allows for low-jitter and low-spur fractional-N operation. The phase-locked loop (PLL), implemented in a standard 28-nm CMOS process, occupies a core area of 0.17 mm^2. It covers a 1-GHz hop to within 70 ppm of the steady-state frequency value in 18.55 μs. The prototype achieves an rms-jitter (integrated from 1 kHz to 100 MHz) of 66.20 and 58.96 fs, in the fractional-N and integer-N modes, respectively. The worst-case in-band fractional spur is at −61 dBc. The total power consumption is 19.8 mW, which leads to a jitter-power figure-of-merit of −250.6 dB for the fractional-N channels

A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter

This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time offset and the narrow range of the sampling phase detector (SPD), which would prevent fractional-N synthesis, a novel digital phase error correction (DPEC) technique, operating in the background, is introduced, which provides robust low-jitter performance. Besides, a novel frequency locking method is presented, which provides fast lock and seamless hand-off to main PLL operation. The PLL has been fabricated in a 28-nm CMOS technology process, and it synthesizes frequencies from 11.9 to 14.1 GHz, achieving an rms jitter of 58.2 and 51.7 fs (integrated into the 1 kHz-100 MHz bandwidth) for a fractional-N and integer-N channel, respectively. The reference spur is as low as -73.5 dBc, while the worst case near-integer fractional spurs are lower than -63.2 dBc. With a power consumption of 18 mW, the jitter-power figure of merit is -252.1 dB (fractional-N) and -253.3 dB (integer-N). The locking time is below 9 μs for a 1-GHz frequency step. The synthesizer occupies 0.16 mm², including decoupling capacitors

A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays

An LO phase-shifting system based on digi- tal fractional-N bang-bang phase-locked loops (PLLs) in the 8.5–10.0-GHz range is presented. A direct phase modulation method is leveraged to perform LO phase-shifting directly within the frequency synthesizer, leading to an inherently linear phase-shifting characteristic, even in the presence of digital-to- time converter (DTC) nonlinearities. Synchronization between fractional-N PLL cores is achieved by clocking with the same reference clock the 16 modulator driving the frequency divider of each core. The adoption of a digital phase-offset correction technique canceling out timing skews greatly simplifies the reference-clock distribution and DTC matching. A dual-core prototype is implemented in a standard 28-nm CMOS process, where each element occupies 0.23-mm2 area and dissipates 20-mW power. An arbitrary phase shift between the LO outputs can be set over the 360◦ range with a resolution of 0.7 millidegree (19 bits). The rms phase accuracy is 0.76°, and the peak-to- peak phase error is 2.1°, without requiring any linearity or gain calibration. Each LO element features a −58.7 dBc in-band fractional spur and a −70 dBc reference spur, with a jitter versus power figure-of-merit of −253.5 and −250.0 dB for integer-N and fractional-N channels, respectively. The combined outputs of the two PLL cores reach an absolute jitter integrated from 1 kHz to 100 MHz (including spurs) of 38.2 and 59.78 fs, in integer-N and near-integer fractional-N operations, respectively

A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL

This paper presents a 14GHz digital-intensive phase modulator circuit, which is able to enforce an arbitrary carrier phase change in one sample of a 200MHz clock. The architecture is based on a fractional-N bang-bang digital PLL exploiting an adaptive DCO-tuning requantizer, which mitigates the segmentation-induced nonlinearity of the DCO, and a novel deskewing circuit, which improves the EVM at high bit rates. The modulation error, expressed in terms of RMS value of the EVM, is below -42dB for a 250Mb/s 32-PSK modulated carrier. The phase modulator, integrated in a 28nm CMOS process, consumes 31.5mW power, achieving 0.13nJ/bit energy consumption